Burst and single error detection and correction system

ABSTRACT

A data communication system has a source of data. The data is divided into data segments. When a burst error is indicated, the location of the burst error is determined and the burst error is corrected. After the burst error has been corrected, the data segment is checked for single bit errors.

United States Patent Blair 1 1 June 26, 1973 1 1 BURST AND SINGLE ERROR DETECTION 3.222.643 l2/l965 Klinkhamer 340/1461 AL AND CORRECTION SYSTEM 3,418,630 12/1968 Van Duuren.... 340/1461 AL 3,478,313 11/1969 Srinivasan 340/1461 AL Inventor: fi s a a 3,542,756 11/1970 Gallager 340/1461 AL I Assigneez Texas Instruments Incorporated 3,544,963 12/1970 Tong 340/1461 AL Dallas, Tex. v Primary ExaminerChar1es E. Atkinson [22] Wed: June 1971 Attorney-Harold Levine, James T. Comfort et a1. [21] App1.No.: 152,824

' [57] ABSTRACT [52] U.S.C1. 340/1461 AL I A data communication system has a source of data. [51] Int. Cl. G06i 11/12 The data is divided into data segments when a burst f 146. [58] Field Search 340/ 1 172 error is indicated, the location of the burst error de- [56] References Cited termmed and the burst error IS corrected. After the UNITED STATES PATENTS burst error has been corrected, the data segment IS checked for single bit errors. 3,487,362 12/1969 ,Frey 340/1461 AL 3,123,803 3/1964 De Lisle et a1. 340/1461 AL 5 Claims, 38 Drawing Figures SIlEIT l li-. SHIFT REC-RTE? 5 PARITY WORD J9 SERIAL GENERATOR OUTPUT 6 won: CONTROL. 6

SERIAL CHECK WORD ERROR RD--D INPUT GENERATOR CORRECTION 7 CONTROL I 4 REA.) F'ARITY WORD REGISTER 53 52'. READ CHECK worm P55 REGISTER 1 I n'rrrA Wm smF-r "11, RM} COUNTETR HTFA WMO 1., COMPARE 'A'iTI-A R00 r IHACK 4 54 ['M ar n p CONTRUI 255A 1 g REGISTER 79 85 I T 51 f-T 5 cMOB I 83 cMon-z -s- I 1 SEE CORRECTION 6'4 7/l PURST -7 TDL'I ERROR DETECT BLC 99, 6 ;..E%? L.,

T MTW W PAIENIEDJIIII26 I975 3m our 26 3 5I2 BIT I WMD SHIFT REGISTER 5.9 PARITY wORO SERIAL GENERATOR OUTPUT WDID CONTROL 66 63 57 SERIAL a CHECK WORD ERROR D P INPUT GENERATOR CORRECTION I" CONTROL 1 k k READ PARITY WORD T 69 REGISTER 53 READ CHECK WORD -55 REGISTER BQTFATWD! SHIFT 6/ 62 QITFA- RM! cOuNTER 93TFA me L .y COMPARE S54 Sc AND L- QSTFA- TRACK BESA S AT I -'CONTROL EESA T b REGISTER -79 5 STA 2 8 T STATI 8/ CMDB I -.1 t

- T STAT 2 83 CMDB -2 .I L

SEE 87 CORRECTION 77 a4 73 TDE ERROR DETECT Ell-C I Fly 1 I I V 56 EEG rmmimuuz 1915 3, m1 02W 26 EXCLU SIV-EOR AND/0R mvsarea SCNTEQZ ma T AT SC NTR ENA SHIFT COUNTER o 1 2 3 4 5 b 7 a 9 0 o 0 0 0 o o o 0 0 SCNTREIQZ 0 o 1 o o o o 1 0 o sc511 o o o 1 1 o 1 o 1 o scs27 1 1 1 1 1 o o 1 1 1 $0537 Fly, 5

PARITY BIT RELATIONSHIP Flag PATENTEDJuu 26 m5 3.742.449

WRITE DATA INPUT (52a CLOCKS) FEEDBACK ENABLE CHECK o 1 z WORD ou'r ENCODER CLOCK Fig /30 READ MESSAGE o 1 2 3 4 s s 7 a- 9 INPUT (538 CLOCKS) 4 DECQDER [35 Fig /3b ERROR SYNDROME MULTIPLIER Fig, /3c

ENCODE TRACK DATA WORD FEEDBACK ENABLE DECODE O I 2 3 4 5 6 7 8 9 TRACK CHECK CODEWORD L35 WORD COMBINED ENCODER/DECODER/MULTIPLIER ou'r Fig, /3d

PAIENIEDJuH26 292s SHEET 150! 26 Y ATBCR ST- PATENTEDJUHZB 1915 3. 742.449

sum 17111 26 ATBCINC F/gl ATBCBO/Q ATBCBI/Q ATEECR ST ATBCEQZ NIB 9 HHEHHBH I O O 0'0 0 I I O O 1 1 1 Q- LOCATORVALUEAT! 1 1 -Q LOCATORVALUEATt a mm o EIIIHBIIIH CWG AT READ FILLING SC538 1 1 1 0 o 1 1 LOCAT'OR VALUE AT SHIFT COUNT ZERO READ C =I O 0 Fig 30 

1. In a data communication system, the combination including a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said record means recording only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator, and means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error.
 2. The combination claimed in claim 1 including means responsive to the detection of a single bit error by said checking means for correcting said single bit error.
 3. In a data communication system, the combination including a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data signal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said recording means recording only one burst error for shifting said data segment out of said shift register one bit at a time, said shift counter responsive to shift of data bits out of said shift register for counting said bits of data, means for comparing the count of bits shifted out of said shift counter with the contents of said burst error address register and indicating a match between them, means responsive to the indication of a match by said comparison means for exclusive oring said data bits and said corresponding parity word to complement said burst errors, and means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error.
 4. The combination claimed in claim 3 including means responsive to the detection of a single bit error by said checking means for correcting said single bit error.
 5. In a data communication system including, a source of data signals, said data signals divided into predetermined segments of binary data, a shift register, means to shift a data segment into said shift register, a parity word generator for generating a parity word from a data segment shifted into said shift register, a shift counter for counting the bits of said data segments shifted into said shift register, means for indicating a burst error in a data segment, means responsive to said indicating means for recording the number of burst errors in said data sigNal, a burst error address register, means responsive to an indication of a burst error for transferring the address of the bit in said data segment at the start of said burst error from said shift counter to said burst error address register, means responsive to said indicating means indicating a burst error and said record means recording only one burst error for correcting the burst error in said data segment at the address indicated in said burst error address register with the parity word generated by said parity word generator, means responsive to the correction of a burst error in a data segment for checking said data segment for a single bit error, each data segment having an associated parity word and a check word, a parity word register, a check word register, means for shifting the parity word associated with said data segment into said parity word register and the check word associated with said data segment into said check word register, a parity error bit counter, a check word generator, means responsive to the correction of a burst error in said data segment by said correction means for feeding said corrected data segment through said parity word generator and said check word generator for detecting a single bit error, said parity error bit counter responsive to the detection of a single bit error for indicating the number of single bit errors in said data segment, and means responsive to the detection of a single bit error for correcting said single bit error in said data segment with said check word generator. 